PHASE LOCKED LOOP CIRCUIT

PURPOSE: A phase locked loop circuit is provided to reduce the unnecessary driving of the phase locked loop circuit by setting a boundary of a buffer for absorbing a jitter and controlling a clock speed. CONSTITUTION: A buffer stores transmission data. A control interface part(11) generates upper and lower alarming information and sampling information. A boundary decision portion(12) determines upper and lower boundaries of the buffer based on the upper and lower alarming information. A sampling decision portion(13) determines a sampling period based on the sampling information. An output control signal generating unit generates an output control signal by comparing the amount of data stored on the buffer with the upper and lower boundaries of the buffer. A FIFO status check portion(14) generates an upper alarming signal if the data of the buffer has an upper boundary; and, otherwise, it generates a lower alarming signal. An OP amp control portion(15) increases a clock speed in response to the upper alarming signal, decreases the clock speed in response to the lower alarming signal, and maintains a current state of the clock speed when none of the alarming signals is generated.