PROCESSOR CONTROLLED COMMAND PORT ARCHITECTURE FOR PLASH MEMORY

PROCESSOR CONTROLLED COMMAND PORT ARCHITECTURE FOR PLASH MEMORY

A semiconductor flash EPROM/EEPROM device includes a command port controller 30, receiving command instructions from a data bus 20 coupled to the memory device 11, to instruct the device to perform read, erase, program, or verify functions, the command port controller generating the necessary contro...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: BAKER, ALAN, WINSTON, MARK, HOEKSTRA, GEORGE, KREIFELS, JERRY A, KYNETT, VIRGILL NEILS, WELLS, STEVEN
Format: Patent
Sprache:eng
Schlagworte:
INFORMATION STORAGE
PHYSICS
STATIC STORES
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Beschreibung
Zusammenfassung:A semiconductor flash EPROM/EEPROM device includes a command port controller 30, receiving command instructions from a data bus 20 coupled to the memory device 11, to instruct the device to perform read, erase, program, or verify functions, the command port controller generating the necessary control signals to cause the memory to function appropriately. By utilizing the command port controller the memory device can be erased and programmed while the device is in the circuit and permits pin compatibility with the prior art EPROM and EEPROMs.