CHAIN CONTROL CIRCUIT FOR MEMORY BLOCK

PURPOSE:To avoid the deterioration of the CPU processing capacity even in such a case many memory blocks are chained for transfer of data by realizing transfer of blocks with no interruption. CONSTITUTION:An address converting circuit 103 serves as a storing part which stores the high-order rank add...

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1. Verfasser: SHIOMI YOSHIHISA
Format: Patent
Sprache:eng
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Zusammenfassung:PURPOSE:To avoid the deterioration of the CPU processing capacity even in such a case many memory blocks are chained for transfer of data by realizing transfer of blocks with no interruption. CONSTITUTION:An address converting circuit 103 serves as a storing part which stores the high-order rank address (a'-c') to give accesses to memory blocks A-C respectively. The addresses of blocks A-C are stored in the circuit 103 functioning as an address conversion table in the chaining order. Thus the data on the blocks A-C set optionally in a memory 106 can be transferred with the automatic block chaining without performing the interruption processing at every transfer of the block. As a result, the CPU processing capacity is never deteriorated even though many memory blocks are chained for the transfer of data.