DYNAMIC TYPE SEMICONDUCTOR MEMORY DEVICE

PURPOSE:To execute refreshment which does not require an external control signal in a reading or a writing cycle and to repeat the access of the same address element by making a refreshing circuit built-in which is activated after reading, writing or refreshing. CONSTITUTION:First, when the inverse of RAS rises, after a delay time only for the completion of the reading, writing or refreshing, a transistor TR 1 separates the RAS with the aid of an output signal phi of a controlled waveform generating circuit 2. Thus, a TR 2n separates an address signal through inverters 5 and 6, a TR 3 connects a semiconductor storage device 1, and activates an address generating circuit 3 and a controlled waveform generating circuit 4. Next, the circuit 3 generates fresh addresses B0-Bm, supplies them to the device 1, and addresses A0-Am are reset by the signal phi. When the refreshment is completed, the process advances to the next cycle. Thus, the same address element can be repeatedly accessed.