COMPOUND SEMICONDUCTOR DEVICE
PURPOSE:To restrain annealing effect, and obtain a deep insulating layer between elements wherein surface leak current is little, by forming a field region in a manner in which a surface layer, a middle layer and a lower layer are formed of the following, respectively; a layer destructed by protons,...
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Format: | Patent |
Sprache: | eng |
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Zusammenfassung: | PURPOSE:To restrain annealing effect, and obtain a deep insulating layer between elements wherein surface leak current is little, by forming a field region in a manner in which a surface layer, a middle layer and a lower layer are formed of the following, respectively; a layer destructed by protons, an impurity introduced layer of second conductivity type, and a layer destructed by protons. CONSTITUTION:A first FET21 and a second FET22 are separated by the following; a surface destruction layer 10 in which surface defect is introduced by proton implantation, a P-type region 11 by boron diffusion, and a lower layer destruction layer 12 in which defect is introduced by proton implantation. The surface destruction layer 10 forms a high resistance layer by high concentration crystal defect, and a new surface level by impurity excitation of boron and the like does not generate, so that the surface leak current can be restrained to a minimum. Further, even if defect recovery by heat annealing in a post-process occurs, its influence is little because the region is small. The P-type region 11 of boron contributes to an insulating region, in the form of a P-N junction or a P-I junction. Further, the destruction layer 12 permeates deeply in the substrate depth direction, and is implanted deeply by comparatively low energy, so that it contributes to making the deep region of a GaAs substrate 1 high resistive, and improves the insulating property. |
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