RING COUNTER

PURPOSE:To attain a stable operation at high speed by synchronizing the input state of the 1st stage flip flop of a pulse generating means with a clock taking the operation timing and setting up it by the next clock when the output state of the setup time setting means is changed. CONSTITUTION:A pul...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: KOSUGI TORU, FURUKAWA TAKAHIRO
Format: Patent
Sprache:eng
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Beschreibung
Zusammenfassung:PURPOSE:To attain a stable operation at high speed by synchronizing the input state of the 1st stage flip flop of a pulse generating means with a clock taking the operation timing and setting up it by the next clock when the output state of the setup time setting means is changed. CONSTITUTION:A pulse generating means 10 being N-stage of cascade connection of a positive output of a 1st flip-flop storing a binary state is given to the input of a 2nd flip-flop storing the binary state, an initial state setting means 20 where a positive output of the N-stage of flip-flops constituting the pulse generating means 10 and its inverted output and a clock having prescribed speed are operated logically so as to set the initial state of the 1st stage flip-flop at a constant state at all times, and a setup time setting means 30 are provided. Then the flipflop is set up at the leading edge of the clock CLK after one period from the time when the input state of the 1st stage flip-flop is decided. Thus, the counter is miniaturized and stable operation is attained even at power application and high speed processing is made possible.