POWER SAVING SYSTEM FOR PROCESSOR

PURPOSE:To save the power to the processor not provided with a sleep mode by providing a clock means on a processing unit composed of a processor, a clock oscillator supplying a clock to the processor and a data input unit. CONSTITUTION:A clock means 7 is started by a signal from a processor 1 and o...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: SAKAMAKI MASAO, YANO HIDEAKI
Format: Patent
Sprache:eng
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Beschreibung
Zusammenfassung:PURPOSE:To save the power to the processor not provided with a sleep mode by providing a clock means on a processing unit composed of a processor, a clock oscillator supplying a clock to the processor and a data input unit. CONSTITUTION:A clock means 7 is started by a signal from a processor 1 and outputs a stop signal to a clock oscillator 8 at the start to stop the clock, thereby inactivating the processor 1. The clock means 7 counts a prescribed time and outputs a restart signal to the clock oscillator 8, which restarts the supply of the clock, then the processor 1 is activated. Then the clock means 7 outputs an interruption signal to the processor 1 and the processor accesses input units 5a-5n to check the presence of input information. Thus, the power consumption is remarkably reduced in the stop time of the clock.