MULTI-CHIP PACKAGING CONSTRUCTION AND TEST THEREOF

PURPOSE: To easily test each chip of a multichip packaging structure by combining the separation of chips to be tested and self-tests with each other. CONSTITUTION: A chip (UUT) to be tested is discriminated from a module. The interference between all other chips from which the UUT is separated and...

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Hauptverfasser: SUKOTSUTO ROURENSU JIYAKOBUSU, BAAHAN OZUMATSUTO, PAAWAATSU NIIHAARU, AASAA RICHIYAADO JINGAA, MARISU TOOMASU MAKUMAAHAN JIYUNIA, HENRIII DANIERU SHIENAAMAN
Format: Patent
Sprache:eng
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Zusammenfassung:PURPOSE: To easily test each chip of a multichip packaging structure by combining the separation of chips to be tested and self-tests with each other. CONSTITUTION: A chip (UUT) to be tested is discriminated from a module. The interference between all other chips from which the UUT is separated and tests is electrically inhibited. The count of all patterns applied upon the UUT is fetched from a memory. A set of pseudo-random or weighted pseudo- random patterns is propagated through the logic circuit of the UUT and becomes a predicted binary value which is found from the output of the UUT. The binary value is outputted from the UUT and accumulated in a signature analyzer and the accumulated result is sent to a comparator. A signature simulated for the UUT is inputted to the comparator from the memory and compared with an actual signature. Therefore, all chips of the module are tested and, when the diagnosis is completed, the process is stopped.