CPU CLOCK SWITCHING METHOD

PURPOSE:To build up a highly reliable system by permitting another CPU to detect an abnormal clock through a dedicated signal line if a clock from a CPU is abnormal or it stops due to a removal in the CPU and switching CPUs so as to output a system clock. CONSTITUTION:Normally a clock signal 16 that...

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Bibliographische Detailangaben
1. Verfasser: WAKITA AKIHIRO
Format: Patent
Sprache:eng
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Zusammenfassung:PURPOSE:To build up a highly reliable system by permitting another CPU to detect an abnormal clock through a dedicated signal line if a clock from a CPU is abnormal or it stops due to a removal in the CPU and switching CPUs so as to output a system clock. CONSTITUTION:Normally a clock signal 16 that a clock generator 13 in the CPU1 generates is outputted to the system clock 10 from an open collector output NAND gate 11. If a clock supervisory unit 14 in the CPU1 detects the abnormality of the clock 16, a clock normal signal 18 comes to a low level, whereas a clock switching signal 14 comes to a high level. In such a way the CPU2 outputs the clock signal to the system clock 10 from the open collector NAND gate 21. When the CPU1 is removed similarly, a pull-up resistance 29 raises the clock switching signal 14 to a high level, and the CPU2 outputs the clock to the system clock 10.