SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE

PURPOSE:To promote the freedom in laying out by a method wherein multiple pairs of two column cells holding a wiring channel of a specified width are arranged with the other wiring channels laid between said pairs. CONSTITUTION:Cell columns Ai and Bi (i=1, 2...4) are arranged respectively holding a...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: KUWANO KAZUSUMI, KORENAGA HIROKI, KAWACHI KAZUYUKI
Format: Patent
Sprache:eng
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Beschreibung
Zusammenfassung:PURPOSE:To promote the freedom in laying out by a method wherein multiple pairs of two column cells holding a wiring channel of a specified width are arranged with the other wiring channels laid between said pairs. CONSTITUTION:Cell columns Ai and Bi (i=1, 2...4) are arranged respectively holding a wiring channel Wo of a specified width between them while the other wiring channels W1, W2 and W3, each made compact to have a specified width required for the wiring according to a wiring program are arranged between the cell columns in respective pair units. C1, C2...Cn representing standard cells with one logical function, counter, etc., previously programed are arranged on respective cell columns Ai, Bi. In such a constitution, in order to lay out the cell columns, the wiring channels W1-W3 can be set up in the specified width required to avoid any shortage of the wiring channels or any waste of cells so that the size of the whole chip may be made smaller as well as the standard cells may be formed extending over the two column cells as necessary to equivalently reduce the length of cell columns by half compared with the conventional one column cell constitution preventing the cell operation from delaying.