OUTPUT TERMINAL TESTING CIRCUIT FOR INTEGRATED CIRCUIT

PURPOSE:To execute a test with few terminals by operating plural gate circuits provided corresponding to the output terminals by staggering the time by means of the output of a shift register in order to execute the continuity test of the plural output terminals on an integrated circuit. CONSTITUTION:A test signal DCT is made a level L at the time of testing. Then output signals of NAND circuits 31-34 produces usually H and data output signals D1-D4 from a logical operation circuit 2 are turned off. Next, output signals Q1-Q4 are set wholly for H by being supplied preset pulse PRST to a shift register 6 and a clock pulse CLCK is thereafter inputted. Therefore the output signals Q1-Q4 are changed to L successively and the NAND circuits 41-44 corresponding to this output signals Q1-Q4 are changed from L to H successively, appearing in output terminals 51-54. Accordingly, existence of defect such as short circuit or disconnection of output terminals 51-54 are inspected by monitoring the level changing.