CONNECTION STRUCTURE OF SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE

A semiconductor chip (10) carrying integrated circuits has lead lines terminating in conductive terminal pads (12) connected to pedestals or bumps (20) extending up from them. Each of the pedestals includes a thin metallic adhesion layer (21) deposited on the pad. A thick metallic layer (22) of alum...

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Bibliographische Detailangaben
Hauptverfasser: SANGU KUUON KANGU, JIEEMUZU GAADONAA RAIAN, MAIKERU JIYON PAAMAA, HARII RANDOORU BITSUKUFUOODO, MAIKERU JIYON BURADEII, ERITSUKU GUREGORI UORUTON, POORU ANDORIYUU MOSUKOUITSUTSU, TEIMOSHII KURAAKU REIRII
Format: Patent
Sprache:eng
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Zusammenfassung:A semiconductor chip (10) carrying integrated circuits has lead lines terminating in conductive terminal pads (12) connected to pedestals or bumps (20) extending up from them. Each of the pedestals includes a thin metallic adhesion layer (21) deposited on the pad. A thick metallic layer (22) of aluminum or an alloy of aluminum is deposited upon said thin metallic adhesion layer. The thick metallic layer forms the bulk of the height of the pedestal. An adhesion layer (23) composed of a thin film of titanium or chromium is deposited on the bump of aluminum . A barrier layer (24) composed of copper, nickel, platinum, palladium, or cobalt is deposited on the adhesion layer. A noble metal (25) consisting of gold, palladium, or platinum is deposited on the barrier layer. Other embodiments disclosed have a modified pedestal structure and/or a variation in the materials used.