JPS6337419B

PURPOSE:To improve the reliability of a multi-processor system without reducing the capacity of data processing by providing each processor module constituting the system with an individual memory and a data transfer channel. CONSTITUTION:Each of processor modules 11-1n connected to a common memory 2 and input/output controlling devices (IOC) 41-4m through a common bus 3 is provided with a processor 111 having an adaptor to control acess to the register of the memory 2 or the IOCs 41-4n, an individual memory 121 to be operated by a command from the processor 111 and a data transfer controlling channel 141 exchanging data between the memory 121 and the memory 2 or IOCs, and these units are connected in parallel through an internal bus 131 mutually. Since the memory 121 is not accessed directly through the bus 3, the memory 121 is not damaged and the channel 141 executes data transfer without the intervention of the processor 11 when a starting command is received from the processor 111, preventing the data processing capacity of each processor from being reduced.