CLOCK CONTROL SYSTEM FOR DATA PROCESSING SYSTEM

PURPOSE:To easily change the clock cycle and to attain an automatic timing margin test of a CPU by providing a timing generating circuit, a timing control circuit, a selection circuit, etc. to the CPU. CONSTITUTION:With input of a microprogram instruction (control signal) 4a, a timing control circuit 4 of a CPU 7 applies such a logic value that validates a clock selection signal -5%, + or -0 or +5%. The output signals 21-23 of the circuit 4 are supplied to a selection circuit 2 and one of clocks 11-13 received from a timing generating circuit 1 is supplied to a clock load circuit via a clock dividing circuit 3. At the same time, the signals 21-23 are supplied to a memory address generating circuit 5. The circuit 5 outputs a memory address in response to an input signal. Thus a clock cycle of the CPU 7 is selected and a selective access is given to a specific address of a memory in accordance with the selected cycle. Then the specific information is written to the specific address. In such a way, a timing margin test is automatically carried out with the CPU 7.