SEMICONDUCTOR INTEGRATED CIRCUIT

PURPOSE:To enable the element layout and inter-element wiring to be made by a mechanical system without increasing the space by a method wherein the active regions of high load driving elements are extended to wiring regions, multiple connecting electrodes are provided on respective logic electrodes...

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1. Verfasser: NUNOGAMI HIROYUKI
Format: Patent
Sprache:eng
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Zusammenfassung:PURPOSE:To enable the element layout and inter-element wiring to be made by a mechanical system without increasing the space by a method wherein the active regions of high load driving elements are extended to wiring regions, multiple connecting electrodes are provided on respective logic electrodes, and layout positions of adjacent rows are slipped off. CONSTITUTION:The high load driving elements comprise the elements on the right side of upper step element row 2 and on the lower step element row 2; source.drain regions 7, 8 of MOSFET and gate electrodes 8 are extended to wiring regions; and the channel width of MOSFET is widened to give high driving capacity. Besides, when both elements laid out on adjacent element row 2 are the high load driving elements, the elements are laid out on slipped off positions not to make the extended source.drain regions 7, 8 shortcircuit with each other. When the elements are laid out on slipped off positions, the automatic layout being made unfeasible due to the slip off from the lattice points used for the inter-element wiring, the electrodes for interelement wiring are provided on the lattice point. Through these procedures, a semiconductor integrated circuit with logic circuit in high driving capacity can be made without increasing the space.