FRAME PHASE SYNCHRONIZING ADJUSTING DEVICE

PURPOSE:To improve a bit buffer circuit with a small capacity and to reduce a circuit scale by counting the hourly distance of the frame phase and the standard frame phase of a receiving signal, judging how many bits are shifted and shifting the receiving signal only for the value. CONSTITUTION:A receiving signal is inputted to a signal line 101, a receiving clock is inputted to a signal line 102, a clock generating circuit 3 outputs a clock without a phase jitter, a bit buffer circuit 1 outputs the receiving signal to attract the phase jitter, and the frame synchronization is established at a frame synchronizing circuit 2. A setting/resetting type flip flop 4 is set by the pulse of the frame phase and reset by the pulse of the standard frame phase from a signal line 106. A counter circuit 6 starts the setting time counting of the flip flop 4, stops the counting at the time point of the resetting, a counted value is held to a latch circuit 7 by the initializing signal from an initializing circuit 5 and inputted to an inverting circuit 8. The output of the inverting circuit 8 is the information to show the number of shiftings and a shift register 9 shifts the output of the bit buffer circuit 1 only by the number of the shiftings and outputs it.