QUICK DATA TRANSMISSION EQUIPMENT

PURPOSE:To improve the response of communication by controlling an equipment so that only correct data blocks can be read into a host computer by a command of an address control part after confirmation of an error code. CONSTITUTION:Data blocks of bit serial are converted to parallel data of byte or word units by a data converting part 2 and are transferred to a prescribed address of a two-port memory 7 by a direct memory access controller (DMAC) 5 set by a microprocessor (mu-p) 6. Successively sent data are stored in the two- port memory 7 similarly. When a data block consisting of a prescribed number of bytes or words is taken into the two-port memory 7, the mu-p 6 checks the data block; and if it is judged as the result that this data block should be transferred to the host computer, the command is outputted to an address control part 9 so that the area of the two-port memory 7 in which the data block is stored can be accessed from the host computer side. Thus, the throughput is improved.