VERTICAL SYNCHRONIZATLON DECISION CIRCUIT

PURPOSE:To compensate non-interlace scanning even for a non interlaced input signal, by performing the discrimination of the non-interlaced input signal by a signal obtained by the logical product of the discrimination pulse of a non- interlace signal and an arriving vertical synchronization detecti...

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1. Verfasser: KOMATSU SUSUMU
Format: Patent
Sprache:eng
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Zusammenfassung:PURPOSE:To compensate non-interlace scanning even for a non interlaced input signal, by performing the discrimination of the non-interlaced input signal by a signal obtained by the logical product of the discrimination pulse of a non- interlace signal and an arriving vertical synchronization detecting signal. CONSTITUTION:A timing signal including a comparison pulse to decide a refer ence mode and a non-reference mode is generated furthermore, and a vertical counter 402 is operated by using a pulse, for example, of 8fH with resolution higher than 2fH as the clock of the vertical counter. And at the time of operat ing a circuit in the reference mode, it is decided whether the arriving vertical synchronization detecting signal 112 is the non-interlace signal by detecting the cycle by the address of the vertical counter and the timing signal. When it is decided as the non-interlace signal as a discriminated result, a mode signal set at the reference mode is inverted, and is switched to the non-reference mode, then, a non-reference operation is performed. In such a way, it is possible to perform an operation without generating erroneous decision for the interlaced input signal.