DIGITAL SIGNAL PROCESSING CIRCUIT

PURPOSE:To reduce power consumption, by inputting the carry output of a first full adder to a second full adder via a first flip-flop, inputting the carry output of a third full adder to a fourth full adder via a second flip-flop, and inputting the sum output of the second full adder to the third full adder. CONSTITUTION:The carry outputs of first adders 51 and 52 are inputted to the first flip-flops 20 and 21, and the outputs of the first flip-flops 20 and 21 are inputted to the second adders 60 and 61, and the carry outputs of the third adders are inputted to the second flip-flops 23 and 24. And the outputs of the second flip-flops are inputted to the fourth adders 63-65, and the sum outputs of the second adders are inputted to the third adders. In such a way, an input signal is outputted with the minimum group delay for the maximum frequency of an inputted digital signal and the frequency of a synchronizing clock, and when a circuit is formed with an LSI, it can be formed with minimum chip size and with resulting minimum power consumption.