LOGIC SIMULATION CONTROL PROCESSING SYSTEM

PURPOSE:To attain a high speed simulation by substituting a register consisting of plural gates for one register part, separating event transmission information from data transmission information and evaluating the information only with either of the leading or trailing of a clock. CONSTITUTION:A register macro converting part 1 converts the register constituted of plural gates included in an original circuit into one register part and at the same time a pseudo clock pattern generation part 3 generates a pseudo clock for prompting the simulation with either of the leading or trailing of the clock. Synchronizing with the pseudo clock, the simulation is executed in state where the event transmission and data transmission are separated by an event data separating part 2 corresponding to an input pattern signal so as to output an output pattern signal. Thus, it may be sufficient that the register part is evaluated once during one clock and moreover the number of evaluating times to the alteration of data is reduced, so that the simulation can be executed at high speed.