BIT SYNCHRONIZING CIRCUIT
PURPOSE:To reduce accidents where data can not be received by converting input burst data in Manchester code into burst data in NRZ code by a decoder then turning off a gate means by a data discriminating means while a period from the detection of a frame pattern in this data to the end of the data....
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Format: | Patent |
Sprache: | eng |
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Zusammenfassung: | PURPOSE:To reduce accidents where data can not be received by converting input burst data in Manchester code into burst data in NRZ code by a decoder then turning off a gate means by a data discriminating means while a period from the detection of a frame pattern in this data to the end of the data. CONSTITUTION:The decoding means 7 converts the input data in Manchester code into the data in NRZ code and the data discriminating means 8 turns off the gate means 9 from the point where the frame pattern in the data is detected to the end of the data. Therefore, even if a phase comparing means 4 applies an H-level signal to the gate means 9 owing to temporary deterioration in the SN ratio of the input data, no edge detection signal is sent out to a D-PLL 6. Consequently, the possibility that a regenerated clock from the D-PLL is locked in wrong phase is improved and the possibility that the data can not be received is reduced. |
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