JPS6316779B

PURPOSE:To decrease a processing time, by directly transferring data from an ROM to an RAM through the compulsive inversion of read/write instruction from a CPU to the RAM, when the address of the ROM and the RAM is partly coincident and the bus is common. CONSTITUTION:An RAM has a memory of e.g., 64-kbyte and 8-kbyte corresponding to addresses 1,000H-2FFFH is commonly possessed with an ROM. In initial program load (IPL) to the common addresses, a read (R) and write (W) signals for the RAM pass through AND/OR circuits. The input to the AND/OR circuits is composed of the said R,W signals and a switching signal so that the R/W from the CPU and the R/N of the RAM can be coincident or replaced. Q=1 is obtained for the FF at the IPL and Q=0 for the other cases. When the address of the ROM and the RAM is coincident, C=1 is detected. Thus, the R is replaced into the W in the RAM with the CPU and the address accessed from the ROM is directly applied to the RAM from the bus 2.