SIMULATION METHOD FOR LOGIC CIRCUIT

PURPOSE:To shorten a period for study of factors by using the inter-block signal change information outputted to a file as a signal input source against each logical block and executing the logical simulation again for each logical block when the working of a logic circuit is searched. CONSTITUTION:...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: MIZOGAMI YOSHITO, KAZAMA YOSHIHARU
Format: Patent
Sprache:eng
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Beschreibung
Zusammenfassung:PURPOSE:To shorten a period for study of factors by using the inter-block signal change information outputted to a file as a signal input source against each logical block and executing the logical simulation again for each logical block when the working of a logic circuit is searched. CONSTITUTION:The data on a simulation subject logic circuit 2 is inputted to a logical simulator 1 together with the signal input data 3 which gives the change of each input signal that checks the circuit 2. Then the signal changes of the circuit 2 are successively calculated and these calculation results are outputted as the simulation output results 4. These results 4 include the connecting information 7 of logical blocks 5 and 6 on the input/output signal names of logical blocks 5 and 6 of the circuit 2 as well as the signal change information 8. In a second execution mode of logical simulation, the circuit data on the block 5 is inputted to the simulator 1 together with the signal change information on the block 5 included in the results 4. Thus the logical simulation of the block 5 is carried out. In such a way, the turn-around time of simulation is shortened.