MULTILAYER INTERCONNECTING METHOD

PURPOSE:To flatten a substrate in structure of multilayer interconnection and to prevent cracks from being generated in a layerinsulation resin layer, by forming an insulating layer on a substrate so as to cover a wiring layer and coating the insulating layer with an insulating resin layer so as to...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
1. Verfasser: KOTANI KOICHIRO
Format: Patent
Sprache:eng
Schlagworte:
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
Beschreibung
Zusammenfassung:PURPOSE:To flatten a substrate in structure of multilayer interconnection and to prevent cracks from being generated in a layerinsulation resin layer, by forming an insulating layer on a substrate so as to cover a wiring layer and coating the insulating layer with an insulating resin layer so as to make the substrate approximately uniform and hardening the insulating resin layer in an atmosphere of plasma so that its etching back to desired thickness is obtained. CONSTITUTION:An element forming layer 2 is made to grow on a substrate 1, and FETs are formed in element isolation regions 3. An insulating layer 6A is formed on the substrate so as to cover a first layered wiring layer 5 formed on the element isolation regions 3. The layer 6A is coated with an insulating resin layer 6B so that thickness of the substrate becomes approximately uniform. A plasma heating process is performed to control film thickness of the insulating resin layer 6 and to flatten the surface of the layer 6. while a resist pattern 8 is used as a mask, etching is performed to form contact holes on the layer-insulation layers 6A and 6B. The resist pattern 8 is coated with a conductive layer 9 for connection all over the surface of the substrate. After the conductive layer 9 is lifted off, the whole surface of the substrate is coated with a SiON layer 10, and the contact holes are opened to expose the conductive layer 9, so that a second layered wiring layer 7 is formed.