FACSIMILE CONTROL PROCESSING SYSTEM

PURPOSE:To attain sure retransmission by providing a delay time detection circuit and a repeat sending time setting circuit setting a time sending a repeat signal corresponding to the detected delay time. CONSTITUTION:The delay time detection circuit 7 detects the delay time of a line connected betw...

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Bibliographische Detailangaben
1. Verfasser: FUKUDA TOSHISHIGE
Format: Patent
Sprache:eng
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Beschreibung
Zusammenfassung:PURPOSE:To attain sure retransmission by providing a delay time detection circuit and a repeat sending time setting circuit setting a time sending a repeat signal corresponding to the detected delay time. CONSTITUTION:The delay time detection circuit 7 detects the delay time of a line connected between a sending side and a receiving side. The repeat sending time setting circuit receiving the notice of the delay time calculates an optimum time width returning a repeat signal to the sending side and sets it. If an error is detected by a CRC calculation circuit 5 in a frame (j) sent from the sending side, the repeat sending time setting circuit receiving the notice of an error signal commands the sending time of a repeat signal having an optimum set time width and sends the result to the sending side via a line. The repeat detection circuit 3 detecting the said repeat signal sends the signal again from the frame (j) detecting the error.