FINE SIGNAL DETECTOR

PURPOSE:To separate and display a fine signal and a larger signal by amplifying a signal received by a reception part at plural levels and taking out a part becoming 'true' at every level. CONSTITUTION:A selection signal logic part 30 compares a signal Dca at a high level as figure E shows...

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Bibliographische Detailangaben
Hauptverfasser: ISHII JUNICHI, SASAKI SOJI
Format: Patent
Sprache:eng
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Beschreibung
Zusammenfassung:PURPOSE:To separate and display a fine signal and a larger signal by amplifying a signal received by a reception part at plural levels and taking out a part becoming 'true' at every level. CONSTITUTION:A selection signal logic part 30 compares a signal Dca at a high level as figure E shows with a signal Dcb at a high level as figure F shows in terms of relationship on a time base. If a time Tca1-Tca2 when the signal Dca is generated is included in a time Tcb1-Tb2 when the signal Dcb is generated, only a signal Dtb at a high level as figure F shows is outputted as a signal Dtc at a high level as figure G shows. Namely, the selection signal logic part 30 calculates the contained relation between a ground Dxa(Txa1 and Txa2) at a high level outputted by the 1st comparator 28 and a group Dyb(Tyb1 and Tyb2) at a high level generated by the 2nd comparator 36. If the Dxa is included in the Dyb, the Dxa is removed, and the output is taken for 'false' (low level).