CONTROL SYSTEM FOR DEBUG INTERRUPTION

PURPOSE:To debug a case including a memory access sequence by using a storing means to store the information word containing the debug interruption control information. CONSTITUTION:The addresses and commands stored in the fields of the ADDR and the CMD of a debug information memory circuit 4 are supplied to the input at one side of each of comparators 7 and 8 via signal lines 401 and 402. While the main memory address 202 and a request command 203 given from a memory access control circuit 2 in an actual memory access mode are applied to the input at the other side of each of comparators 7 and 8. The pointer information on a PNT field is supplied to the input at one side of a switch circuit 6. Thus the pointer information on the PNT field is selected only in case the addresses of the memory request are coincident and the commands are dissident respectively. In other cases, the value obtained by adding 1 to the contents of an address pointer 5 is selected.