METHOD FOR POSITIONING SEMICONDUCTOR CHIP

PURPOSE:To eliminate factors responsible for degraded quality, decreased yield, and lowered facilities commission rate by a method wherein a positioning jig tip located on an alignment stage is inserted into a vacuum hole whereinto a guide pin is inserted for the positioning of the tip and the fixed...

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1. Verfasser: SASAKI KAZURO
Format: Patent
Sprache:eng
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Zusammenfassung:PURPOSE:To eliminate factors responsible for degraded quality, decreased yield, and lowered facilities commission rate by a method wherein a positioning jig tip located on an alignment stage is inserted into a vacuum hole whereinto a guide pin is inserted for the positioning of the tip and the fixed by adjusting fingers. CONSTITUTION:An alignment stage 1 is provided with a vacuum hole 2 leading to a vacuum device. A positioning jig tip 5 with its sides longer than a chip by approximately 10-30mum is installed on the alignment stage 1. Through a hole provided at the center of the tip 5, a guide pin 6 is inserted into the vacuum hole 2 for positioning the tip 5. The guide pin 6 is smaller in diameter than the vacuum hole 2 by approximately 50mu and is tapered toward its point. A pair of adjusting fingers 3, with its fixing screw 4 loosened beforehand, is positioned to grasp the tip 5 on its both sides, and then the fixing screw 4 is tightened. This enables the positional alignment of the tip 5 to the center of the vacuum hole 2 to be accomplished simultaneously with the adjustment of the gap between the adjusting fingers 3 and the tip 5.