COUNTER CIRCUIT WITH TEST FUNCTION

PURPOSE:To realize a counter circuit with test function by the number of control inputs less than that of a conventional circuit by providing a clear circuit clearing automatically the circuit after the end of data sampling. CONSTITUTION:The clear signal 48 of a counter 46 goes to 'L' by b...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: YANO SHIGEKI, MIYAGAWA KATSUHIKO
Format: Patent
Sprache:eng
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Beschreibung
Zusammenfassung:PURPOSE:To realize a counter circuit with test function by the number of control inputs less than that of a conventional circuit by providing a clear circuit clearing automatically the circuit after the end of data sampling. CONSTITUTION:The clear signal 48 of a counter 46 goes to 'L' by bringing the level of enable signals 45, 44 to 'H' and 'L' respectively at a circuit test and a test input 43 is inputted to a counter 46. When the input of the circuit test is finished, the set input 51 of a shaft register 50 goes to 'H' by bringing the level of the enable signal 45 to 'L' to store a data just before. The stored data is a serial signal by inputting a clock to the shift input 52 of the shift register 50 and the circuit operation is tested by collating the said output with the inputted test pulse number.