CACHE MEMORY AND CACHE MEMORY SYSTEM USING SAID CACHE MEMORY

PURPOSE:To obtain a 1-chip cache memory by allocating blocks with a cache memory chip when a start signal is applied to a block loading start terminal. CONSTITUTION:In case a block including an address having a request for access exists on an own cache memory (data memory 14), i.e., in a hit mode, t...

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Bibliographische Detailangaben
Hauptverfasser: ONO NAOYA, IKEDA SADANOBU
Format: Patent
Sprache:eng
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Zusammenfassung:PURPOSE:To obtain a 1-chip cache memory by allocating blocks with a cache memory chip when a start signal is applied to a block loading start terminal. CONSTITUTION:In case a block including an address having a request for access exists on an own cache memory (data memory 14), i.e., in a hit mode, the value '1' is delivered to a coincidence terminal FS. At the same time, a replacement circuit 15 is replaced by the coincidence detecting address FBA delivered from a directory 12. While an access is given to the memory 14 in the same way with the values of the block address FBA delivered from the directory 12 and in an intra-block word address of an address register 11 used as addresses. In other words, the memory 14 is read if the access request indicates a reading mode. This read-out value is stored in a reading data register 16. Then the output of the register 16 is applied to a processor data terminal PD and a signal is applied to a processor access terminal PC to show that the access is through.