METHOD AND APPARATUS FOR BLOCK ENCODING AND DECODING

PURPOSE:To improve the S/N by operating the operation in the 7-bit PCM mode when the least weight bit of an 8-bit PCM code subjected to block decoding is missing and the other high-order 7-bit is reproduced correctly. CONSTITUTION:An 8-bit nonlinear PCM signal inputted from a terminal 5 is inputted...

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1. Verfasser: AIKO SHINICHI
Format: Patent
Sprache:eng
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Zusammenfassung:PURPOSE:To improve the S/N by operating the operation in the 7-bit PCM mode when the least weight bit of an 8-bit PCM code subjected to block decoding is missing and the other high-order 7-bit is reproduced correctly. CONSTITUTION:An 8-bit nonlinear PCM signal inputted from a terminal 5 is inputted to a delay circuit 10 and a maximum value detection circuit 20 at the transmission side, the circuit 10 gives a delay for one block length and a maximum value in the block is detected by the circuit 20 during that period. A separation circuit 50 separates maximum value information and a sample code at a separation circuit 50 at the reception side, the maximum value information is held by a register 70 by one block time and the sample code is restored by a decoder 60 into an 8-bit PCM code accordingly. In this case, When it is discriminated by a discrimination circuit 80 that the least weight bit of the 8-bit PCM code subjected to block decoding is missing and the other high-order 7-bit is reproduced correctly, the operation is executed in the 7-bit PCM mode. Thus, the S/N is improved.