SEMICONDUCTOR DEVICE

PURPOSE:To extend a gate control range by partly forming the second conductivity type semiconductor region of high impurity region corresponding to the first conductivity type region on the other surface of a substrate, and spacing an interval between the bottom of the second conductivity type region and the first conductivity type drain semiconductor layer. CONSTITUTION:Since a P type drain/collector region 70 is partly formed on the other surface of an N type drain/collector layer 10 directly under N type source/emitter region 4 and an N type buffer layer 100 is formed on the bottom surface of the P type drain/collector region 70, holes are partly implanted from the region 70 to a drain drift layer 6, and the implanting is suppressed by the layer 100. Thus, the DC current amplification factor hFE of a parasitic PNP transistor is decreased, voltage drops Vs of the P-type base region and P type base central region 50 of the transistor reduce, thereby increasing a gate control range.