BIPOLAR MEMORY CELL

An integrated bipolar memory cell with random access, includes an upper word line, a lower word line, two bit lines, two transistors each having two emitters, a base and a collector fed back crosswise to the base of the other transistor, two Schottky diodes, two low-resistance load resistors each forming a series circuit with a respective one of the Schottky diodes, two high-resistance load resistors each forming a parallel circuit with a respective one of the series circuits, each of the parallel circuits being connected between a respective one of the collectors and the upper word line defining active regions of the memory cell, one of the emitters of each of the transistors being connected to the lower word line, the other of the emitters of each of the transistors being connected to a respective one of the bit lines, and an external capacitance connected between the collectors outside the active regions.