JPS6245575B

PURPOSE:To prevent an unnecessary advance in program step and realize efficient interfacing without spoiling the compatibility of a control program by processing a stack status through an interface control circuit. CONSTITUTION:A host CPU1 is provided with a byte multiplexer 1-1 and a communication...

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1. Verfasser:	HIGUCHI TAIHO
Format:	Patent
Sprache:	eng
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC COMMUNICATION TECHNIQUE ELECTRIC DIGITAL DATA PROCESSING ELECTRICITY PHYSICS TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION
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creator	HIGUCHI TAIHO
description	PURPOSE:To prevent an unnecessary advance in program step and realize efficient interfacing without spoiling the compatibility of a control program by processing a stack status through an interface control circuit. CONSTITUTION:A host CPU1 is provided with a byte multiplexer 1-1 and a communication controller 2 connected to a communication circuit 3 is connected to the CPU1. This controller 2 is provided with an arithmetic part 2-1, circuit scanner 2-2, memory 2-3, and interface control circuit 2-4. Further, the control circuit 2-4 is provided with a status register 4-1 which transfers data to and from the channel 1-1, and with subchannel register 4-2, status memory 4-3, status transmission control circuit 4-4, status control latch group 4-5, etc. Then, the stack status is processed by the control circuit 2-4 to eliminate an unnecessary advance in program step, and to realize the efficient interfacing without spoiling the compatibility of the control program.
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CONSTITUTION:A host CPU1 is provided with a byte multiplexer 1-1 and a communication controller 2 connected to a communication circuit 3 is connected to the CPU1. This controller 2 is provided with an arithmetic part 2-1, circuit scanner 2-2, memory 2-3, and interface control circuit 2-4. Further, the control circuit 2-4 is provided with a status register 4-1 which transfers data to and from the channel 1-1, and with subchannel register 4-2, status memory 4-3, status transmission control circuit 4-4, status control latch group 4-5, etc. Then, the stack status is processed by the control circuit 2-4 to eliminate an unnecessary advance in program step, and to realize the efficient interfacing without spoiling the compatibility of the control program.</description><language>eng</language><subject>CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC COMMUNICATION TECHNIQUE ; ELECTRIC DIGITAL DATA PROCESSING ; ELECTRICITY ; PHYSICS ; TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION</subject><creationdate>1987</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=19870928&DB=EPODOC&CC=JP&NR=S6245575B2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76289</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=19870928&DB=EPODOC&CC=JP&NR=S6245575B2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>HIGUCHI TAIHO</creatorcontrib><title>JPS6245575B</title><description>PURPOSE:To prevent an unnecessary advance in program step and realize efficient interfacing without spoiling the compatibility of a control program by processing a stack status through an interface control circuit. CONSTITUTION:A host CPU1 is provided with a byte multiplexer 1-1 and a communication controller 2 connected to a communication circuit 3 is connected to the CPU1. This controller 2 is provided with an arithmetic part 2-1, circuit scanner 2-2, memory 2-3, and interface control circuit 2-4. Further, the control circuit 2-4 is provided with a status register 4-1 which transfers data to and from the channel 1-1, and with subchannel register 4-2, status memory 4-3, status transmission control circuit 4-4, status control latch group 4-5, etc. Then, the stack status is processed by the control circuit 2-4 to eliminate an unnecessary advance in program step, and to realize the efficient interfacing without spoiling the compatibility of the control program.</description><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC COMMUNICATION TECHNIQUE</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>ELECTRICITY</subject><subject>PHYSICS</subject><subject>TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>1987</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZOD2Cgg2MzIxNTU3deJhYE1LzClO5YXS3AxKbq4hzh66qQX58anFBYnJqXmpJfFIOpyMjIlSBACGtBx7</recordid><startdate>19870928</startdate><enddate>19870928</enddate><creator>HIGUCHI TAIHO</creator><scope>EVB</scope></search><sort><creationdate>19870928</creationdate><title>JPS6245575B</title><author>HIGUCHI TAIHO</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_JPS6245575BB23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>1987</creationdate><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC COMMUNICATION TECHNIQUE</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>ELECTRICITY</topic><topic>PHYSICS</topic><topic>TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION</topic><toplevel>online_resources</toplevel><creatorcontrib>HIGUCHI TAIHO</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>HIGUCHI TAIHO</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>JPS6245575B</title><date>1987-09-28</date><risdate>1987</risdate><abstract>PURPOSE:To prevent an unnecessary advance in program step and realize efficient interfacing without spoiling the compatibility of a control program by processing a stack status through an interface control circuit. CONSTITUTION:A host CPU1 is provided with a byte multiplexer 1-1 and a communication controller 2 connected to a communication circuit 3 is connected to the CPU1. This controller 2 is provided with an arithmetic part 2-1, circuit scanner 2-2, memory 2-3, and interface control circuit 2-4. Further, the control circuit 2-4 is provided with a status register 4-1 which transfers data to and from the channel 1-1, and with subchannel register 4-2, status memory 4-3, status transmission control circuit 4-4, status control latch group 4-5, etc. Then, the stack status is processed by the control circuit 2-4 to eliminate an unnecessary advance in program step, and to realize the efficient interfacing without spoiling the compatibility of the control program.</abstract><oa>free_for_read</oa></addata></record>
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subjects	CALCULATING COMPUTING COUNTING ELECTRIC COMMUNICATION TECHNIQUE ELECTRIC DIGITAL DATA PROCESSING ELECTRICITY PHYSICS TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION
title	JPS6245575B
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