DPLL NO INPUT SIGNAL COMPENSATION CIRCUIT

PURPOSE:To attain immediate data demodulation and carrier extraction when an input signal is lost and restored again by using a gate circuit to control a signal from a counter circuit so as not to send a signal to a pulse addition/ elimination circuit. CONSTITUTION:In a DPLL circuit comprising a pha...

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1. Verfasser: ASAKA KAZUHIKO
Format: Patent
Sprache:eng
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Zusammenfassung:PURPOSE:To attain immediate data demodulation and carrier extraction when an input signal is lost and restored again by using a gate circuit to control a signal from a counter circuit so as not to send a signal to a pulse addition/ elimination circuit. CONSTITUTION:In a DPLL circuit comprising a phase comparator 1, a counter circuit 2 controlled by a signal from the phase comparator 1, a pulse addition/ elimination circuit 6 controlled by a signal from the counter circuit 2 and an oscillator 7 supplying a signal to the counter circuit 2 and the pulse addition/ elimination circuit 6, an input signal detection circuit 3 detecting an input signal to the DPLL and a gate circuit 4 controlling the signal transmission between the counter circuit 2 and the pulse addition/elimination circuit 6 and controlled by the input signal detection circuit 3 are provided. Thus, if the input signal is lost and then restored again, the data demodulation and carrier extraction are attained immediately.