SEMICONDUCTOR DEVICE
PURPOSE:To facilitate power interconnection and enable a completely automatic layout, by disposing large-scale cells along four sides of a chip and disposing standard cells in row structure. CONSTITUTION:I/O cells 2 are disposed along the periphery of a chip. As to cells 3-6, the cell 3 is disposed...
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creator | ISHII JUNICHI HATANO YOSHINORI KAWACHI KAZUYUKI |
description | PURPOSE:To facilitate power interconnection and enable a completely automatic layout, by disposing large-scale cells along four sides of a chip and disposing standard cells in row structure. CONSTITUTION:I/O cells 2 are disposed along the periphery of a chip. As to cells 3-6, the cell 3 is disposed on the upper left corner of the chip 1, and the cell 6 is disposed on the lower left corner, and the cell 4 is disposed adjacent to and to the right of the cell 3 and along the cells 2, and the cell 5 is disposed on the lower adjacent side of the cell 3 and along the cells 2. In the region except the one where the cells 3-6 and 2 are disposed on the chip 1, standard cells 7 are disposed in lines with respective different lengths in height directions. Such disposal facilitates power interconnection and enables a completely automatic layout. |
format | Patent |
fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_JPS62264639A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>JPS62264639A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_JPS62264639A3</originalsourceid><addsrcrecordid>eNrjZBAJdvX1dPb3cwl1DvEPUnBxDfN0duVhYE1LzClO5YXS3AyKbq4hzh66qQX58anFBYnJqXmpJfFeAcFmRkZmJmbGlo7GxKgBAIv-Hw4</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>SEMICONDUCTOR DEVICE</title><source>esp@cenet</source><creator>ISHII JUNICHI ; HATANO YOSHINORI ; KAWACHI KAZUYUKI</creator><creatorcontrib>ISHII JUNICHI ; HATANO YOSHINORI ; KAWACHI KAZUYUKI</creatorcontrib><description>PURPOSE:To facilitate power interconnection and enable a completely automatic layout, by disposing large-scale cells along four sides of a chip and disposing standard cells in row structure. CONSTITUTION:I/O cells 2 are disposed along the periphery of a chip. As to cells 3-6, the cell 3 is disposed on the upper left corner of the chip 1, and the cell 6 is disposed on the lower left corner, and the cell 4 is disposed adjacent to and to the right of the cell 3 and along the cells 2, and the cell 5 is disposed on the lower adjacent side of the cell 3 and along the cells 2. In the region except the one where the cells 3-6 and 2 are disposed on the chip 1, standard cells 7 are disposed in lines with respective different lengths in height directions. Such disposal facilitates power interconnection and enables a completely automatic layout.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>1987</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=19871117&DB=EPODOC&CC=JP&NR=S62264639A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=19871117&DB=EPODOC&CC=JP&NR=S62264639A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>ISHII JUNICHI</creatorcontrib><creatorcontrib>HATANO YOSHINORI</creatorcontrib><creatorcontrib>KAWACHI KAZUYUKI</creatorcontrib><title>SEMICONDUCTOR DEVICE</title><description>PURPOSE:To facilitate power interconnection and enable a completely automatic layout, by disposing large-scale cells along four sides of a chip and disposing standard cells in row structure. CONSTITUTION:I/O cells 2 are disposed along the periphery of a chip. As to cells 3-6, the cell 3 is disposed on the upper left corner of the chip 1, and the cell 6 is disposed on the lower left corner, and the cell 4 is disposed adjacent to and to the right of the cell 3 and along the cells 2, and the cell 5 is disposed on the lower adjacent side of the cell 3 and along the cells 2. In the region except the one where the cells 3-6 and 2 are disposed on the chip 1, standard cells 7 are disposed in lines with respective different lengths in height directions. Such disposal facilitates power interconnection and enables a completely automatic layout.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>1987</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZBAJdvX1dPb3cwl1DvEPUnBxDfN0duVhYE1LzClO5YXS3AyKbq4hzh66qQX58anFBYnJqXmpJfFeAcFmRkZmJmbGlo7GxKgBAIv-Hw4</recordid><startdate>19871117</startdate><enddate>19871117</enddate><creator>ISHII JUNICHI</creator><creator>HATANO YOSHINORI</creator><creator>KAWACHI KAZUYUKI</creator><scope>EVB</scope></search><sort><creationdate>19871117</creationdate><title>SEMICONDUCTOR DEVICE</title><author>ISHII JUNICHI ; HATANO YOSHINORI ; KAWACHI KAZUYUKI</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_JPS62264639A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>1987</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>ISHII JUNICHI</creatorcontrib><creatorcontrib>HATANO YOSHINORI</creatorcontrib><creatorcontrib>KAWACHI KAZUYUKI</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>ISHII JUNICHI</au><au>HATANO YOSHINORI</au><au>KAWACHI KAZUYUKI</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>SEMICONDUCTOR DEVICE</title><date>1987-11-17</date><risdate>1987</risdate><abstract>PURPOSE:To facilitate power interconnection and enable a completely automatic layout, by disposing large-scale cells along four sides of a chip and disposing standard cells in row structure. CONSTITUTION:I/O cells 2 are disposed along the periphery of a chip. As to cells 3-6, the cell 3 is disposed on the upper left corner of the chip 1, and the cell 6 is disposed on the lower left corner, and the cell 4 is disposed adjacent to and to the right of the cell 3 and along the cells 2, and the cell 5 is disposed on the lower adjacent side of the cell 3 and along the cells 2. In the region except the one where the cells 3-6 and 2 are disposed on the chip 1, standard cells 7 are disposed in lines with respective different lengths in height directions. Such disposal facilitates power interconnection and enables a completely automatic layout.</abstract><oa>free_for_read</oa></addata></record> |
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subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
title | SEMICONDUCTOR DEVICE |
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