COMPUTER SYSTEM

PURPOSE:To connect plural processors, or peripheral units having different processing speeds, by providing a circuit to frequency-divide an input clock signal, and a clock selection circuit. CONSTITUTION:The input clock signal is supplied from the clock output terminal CO of a microprocessor MPU that becomes a host computer, to the clock input terminal C1 of a peripheral unit PDU. When the PDU is operated asynchronously and independently from the MPU, a crystal oscillator Xta1 is connected. The input clock signal inputted to the terminal C1, is supplied to a clock generation circuit CG, and the circuit CG performs the waveform arrangement of the input clock signal, and forms a fundamental clock signal. The fundamental clock signal is inputted to a 1/2 frequency-dividing circuit 1/2CD, then a 1/2 frequency-dividing clock signal is formed. The fundamental clock signal, and the 1/2 frequency-dividing clock signal are selected respectively through each of switches Q1 and Q2, and they are supplied to an internal device as internal clock signals CP, and also, they are supplied to an external device through a clock output terminal C3.