PHASE COMPARATOR

PURPOSE:To obtain a phase comparator having equal UP/DOWN pulse width by using three logic elements of one kind having the same delay time. CONSTITUTION:FFs 21, 22, 26 are D edge trigger FFs, an UP signal 11 goes to an H level in a time T0 after the leading edge of a data 8, a DOWN signal 12 goes to an H level in a time T0 after the leading edge of a clock 18 and the UP signal 11 goes to an L level after a time T1 further. A Reset DOWN signal 25 goes to an L level in a time T0 after the leading of an inversion 27 of the clock 18 and the DOWN signal 12 goes to an L level after the time T1, then a series of operation is finished. In comparing the pulse width of the UP signal 11 and the DOWN signal 12, the delay time till the leading edge is T0 and the delay time up to the trailing is T0+T1, and the duty cycle of the clock 18 is 50%, and when the phase difference between the clocks 18, 27 is 180 deg., both the pulse widths are equal to each other.