CONTROL SYSTEM FOR INTER-PROCESSOR TRANSFER OF DATA
PURPOSE:To attain the simple transfer of data by preparing both master and slave processors to secure the bidirectional transfer of data between both processors so that the data transfer request is controlled by the master processor. CONSTITUTION:Data are transferred between a master processor MP an...
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creator | HAMAGUCHI KAZUHIKO |
description | PURPOSE:To attain the simple transfer of data by preparing both master and slave processors to secure the bidirectional transfer of data between both processors so that the data transfer request is controlled by the master processor. CONSTITUTION:Data are transferred between a master processor MP and a slave processor SP. Then the master data transfer means 3-1-3-n and the slave data transfer means 6-1-6-n can transfer data in both directions via the data transfer paths SP-1-SP-n which are set statically. Furthermore a master control means 2 set at the MP side controls all data transfer requests given from both processors MP and SP. |
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CONSTITUTION:Data are transferred between a master processor MP and a slave processor SP. Then the master data transfer means 3-1-3-n and the slave data transfer means 6-1-6-n can transfer data in both directions via the data transfer paths SP-1-SP-n which are set statically. Furthermore a master control means 2 set at the MP side controls all data transfer requests given from both processors MP and SP.</description><language>eng</language><subject>CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; PHYSICS</subject><creationdate>1987</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=19871005&DB=EPODOC&CC=JP&NR=S62226265A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=19871005&DB=EPODOC&CC=JP&NR=S62226265A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>HAMAGUCHI KAZUHIKO</creatorcontrib><title>CONTROL SYSTEM FOR INTER-PROCESSOR TRANSFER OF DATA</title><description>PURPOSE:To attain the simple transfer of data by preparing both master and slave processors to secure the bidirectional transfer of data between both processors so that the data transfer request is controlled by the master processor. CONSTITUTION:Data are transferred between a master processor MP and a slave processor SP. Then the master data transfer means 3-1-3-n and the slave data transfer means 6-1-6-n can transfer data in both directions via the data transfer paths SP-1-SP-n which are set statically. Furthermore a master control means 2 set at the MP side controls all data transfer requests given from both processors MP and SP.</description><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>PHYSICS</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>1987</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZDB29vcLCfL3UQiODA5x9VVw8w9S8PQLcQ3SDQjyd3YNDgbyQ4Ic_YLdXIMU_N0UXBxDHHkYWNMSc4pTeaE0N4Oim2uIs4duakF-fGpxQWJyal5qSbxXQLCZkZGRmZGZqaMxMWoAxqMnoA</recordid><startdate>19871005</startdate><enddate>19871005</enddate><creator>HAMAGUCHI KAZUHIKO</creator><scope>EVB</scope></search><sort><creationdate>19871005</creationdate><title>CONTROL SYSTEM FOR INTER-PROCESSOR TRANSFER OF DATA</title><author>HAMAGUCHI KAZUHIKO</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_JPS62226265A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>1987</creationdate><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>PHYSICS</topic><toplevel>online_resources</toplevel><creatorcontrib>HAMAGUCHI KAZUHIKO</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>HAMAGUCHI KAZUHIKO</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>CONTROL SYSTEM FOR INTER-PROCESSOR TRANSFER OF DATA</title><date>1987-10-05</date><risdate>1987</risdate><abstract>PURPOSE:To attain the simple transfer of data by preparing both master and slave processors to secure the bidirectional transfer of data between both processors so that the data transfer request is controlled by the master processor. CONSTITUTION:Data are transferred between a master processor MP and a slave processor SP. Then the master data transfer means 3-1-3-n and the slave data transfer means 6-1-6-n can transfer data in both directions via the data transfer paths SP-1-SP-n which are set statically. Furthermore a master control means 2 set at the MP side controls all data transfer requests given from both processors MP and SP.</abstract><oa>free_for_read</oa></addata></record> |
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subjects | CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS |
title | CONTROL SYSTEM FOR INTER-PROCESSOR TRANSFER OF DATA |
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