EXPANSION ADDRESS CONVERTER

PURPOSE:To shorten an address conversion time by selecting an entry coinciding with the longest part of virtual addresses out of an entry group registered in a converting buffer device and outputting one table in a head converting table group or a real address. CONSTITUTION:An instruction part 101 r...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: KAGIMASA TOYOHIKO, GOTO SHIZUO
Format: Patent
Sprache:eng
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Beschreibung
Zusammenfassung:PURPOSE:To shorten an address conversion time by selecting an entry coinciding with the longest part of virtual addresses out of an entry group registered in a converting buffer device and outputting one table in a head converting table group or a real address. CONSTITUTION:An instruction part 101 read from a main memory device 400 is supplied from an instruction analysis control part 100 to an instruction execution part 200 and a virtual address 2 calculated by an address calculating part 210 is outputted to an address conversion part 230. The conversion table having hierarchical structure for converting the address 2 into a real address is stored in the device 400 and specified by a register 1 in a control register control part 240. The leading address group of the conversion table is stored in the conversion buffer 20 together with the pair of the virtual address and the real address and the entry coinciding with the longest part of the virtual address is selected from the entry group registered in the buffer 20 by a level determining/selecting circuit 30. One head conversion table out of the head conversion table group or the real address is outputted in accordance with the coincident length, so that the conversion time can be shortened.