INTEGRATED CIRCUIT

PURPOSE:To decrease the number of signal lines and transistor TR by delivering the contents of a muROM or a PLA to an internal bus with use of a NMOS TR and a PMOS TR having the threshold voltage higher than the 1st power supply voltage as the gates. CONSTITUTION:Power supplies 11a, 12a and 15a are kept at the level of the 1st voltage 5V in a normal working mode. Thus a special output gate 15 is kept at a high impedance when viewed from the side of an internal bus 14. Then the contents of both registers 1 and 2 are delivered to the bus 14 under the control of control signals 4 and 5. When the output of contents is desired with a muROM or a PLA 3, an integrated circuit is reset and therefore both signals 4 and 5 are set at logic 'L'. While the tri-state output buffers 11 and 12 are set under a high impedance state. Therefore, both a NMOS TR and a PMOS TR in the gate 15 are actuated when the power supply 15a is set at a high level. Then the contents of the muROM or the PLA 3 can be read out to the bus 14.