GENERATING SYSTEM FOR PARITY DATA

PURPOSE:To eliminate the troublesomeness caused by a conventional parity data generating system and to omit the consideration given to the parity data when a programs is changed or developed, by producing the parity data on the program stored in a ROM through a controller itself. CONSTITUTION:In the application mode of power supply, a RAM read/write control circuit 10 is set under a RAM write mode by the power supply application signal 14. While the RAM write permission signal 12 is produced and inputted to the WE line of a parity data storing RAM 9. Thus the parity data can be written to the RAM 9. Under such conditions, a processor 1 reads a program out of a program storing ROM 2 and then reads the entire area of the ROM 2 based on said program. Then the parity data 6 generated by a parity generating circuit 3 is written to the RAM 9 as soon as the program is read out. Thus the parity data is produced within the RAM 9.