SEMICONDUCTOR MEMORY

PURPOSE:To operate the titled memory in a stable manner by substantially reducing the potential difference between the earthing point and an earthing wire of the memory cell by a method wherein adjoining word wire or earthing wire arranged in row (or in column) are connected in a crossing form in the center point or in its vicinity between the earthing wires provided for the column (or row) of a plurality of memory cells. CONSTITUTION:One of electrodes of the first and the second read-out and write-in transistors A1-H1 and A2-H2 are connected to memory cells MA-MH respectively, and other electrodes are connected to column, and they are used as the first and the second bit wires (d) and (-d). Then, the memory cells are formed into connection wires 4 and 6 by connecting the earthed points of the memory cells MA-MH for every row, the connection wires 4 and 6 are connected for every column (4 columns here) of the prescribed number of memory cells, and they are formed into earthing wires 1 and 2. Also, the earthing wires 1 and 2 are wires in such a manner that they make a crossing form for every pair of rows adjoining in the center point of the earthing wires 1 and 2, the gates of the first and the second read-out and wirte-in transistors A1-B2, C1-D2, E1-F2 and G1-H2 are connected common in row direction, and they are constituted as word wires 3 and 5.