INPUT CIRCUIT FOR SEMICONDUCTOR INTEGRATED CIRCUIT

PURPOSE:To eliminate the noise at the time of rise and fall of an input signal by forming an input circuit by a delay circuit, a logic circuit and a flip-flop circuit. CONSTITUTION:The logic circuit comprising a buffer circuit 13, a delay circuit 14, a 2-input AND circuit 15 and a 2-input NOR circui...

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1. Verfasser: SHIDEI TSUNAAKI
Format: Patent
Sprache:eng
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Zusammenfassung:PURPOSE:To eliminate the noise at the time of rise and fall of an input signal by forming an input circuit by a delay circuit, a logic circuit and a flip-flop circuit. CONSTITUTION:The logic circuit comprising a buffer circuit 13, a delay circuit 14, a 2-input AND circuit 15 and a 2-input NOR circuit 16, and a set/reset type flip-flop circuit 17 are connected between input and output terminals 11 and 12. The delay circuit 14 retards the input signal, the logic circuits 15, 16 form a set signal and a reset signal from the input signal and the retarded input signal, the set signal and the reset signal change the operating state of the flip-flop circuit 17 to send an output signal. In this case, the noise included in the input signal is eliminated by the delay operation by the delay circuit and the operating timing of the flip-flop circuit to obtain a stable output signal.