HOLD TIME MONITOR CIRCUIT

PURPOSE:To prevent a main processor from being in the hold state for a long time to break down a system by monitoring the hold time of the main processor by a timer which generates a time-up signal after a prescribed time. CONSTITUTION:A timer means 103 discriminates the hold start of a main process...

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1. Verfasser: OSAWA CHIHARU
Format: Patent
Sprache:eng
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Zusammenfassung:PURPOSE:To prevent a main processor from being in the hold state for a long time to break down a system by monitoring the hold time of the main processor by a timer which generates a time-up signal after a prescribed time. CONSTITUTION:A timer means 103 discriminates the hold start of a main processor 101 in accordance with the output of AND between a hold request signal from a subprocessor 102 to the main processor 101 and a hold response signal, which is outputted from the main processor 101 to the subprocessor 102 in response to the hold request signal, to start measuring the hold time, and the time-up signal is generated and is supplied to a reset signal generating means 104 when a prescribed hole monitor time elapses. The reset signal generating means 104 resets the subprocessor, which issues the hold request signal, on a basis of this time-up signal.