COMPLEMENTARY LSI CHIP

PURPOSE:To improve the degree of integration in interconnection channel region by a method wherein p,n channel device regions are separated to be alternately turned back while chennels are cut on the turning back parts of Si substrate to bury power supply lines therein. CONSTITUTION:A power supply line VSS is buried in a channel H1 between an n-ch FET26 and an adjoining n-ch element with an insulating layer 27 on a p type Si substrate 21 to provide an insulating film INS forming an interconnection channel WR1. Likewise another power supply line VDD is buried in a channel 2 between a p-ch FETs 25 and 24 with another insulating layer 29 to provide the insulating film INS forming another interconnection channel WR2. The power supply lines VSS, VDD are made of Al. An n layer 22 is provided below a power supply line VDD to prevent current from leaking in a p type Si substrate 21. Furthermore, channels h1, h2 narrower than the channels H1, H2 are cut between FETs 26 and 25 to bury insulating films 28, 30 therein forming an interelement separating region ISO. In such a constitution, the interconnection channel can be formed around 100mum thick so that the power supply lines buried therein may be formed sufficiently wider to prevent any troubles such as electromigration etc. from occurring to improve the degree of integration.