FRAME SYNCHRONIZER

PURPOSE:To obtain a frame synchronizer almost hardly giving effect on a pattern by switching a memory plane having an error into that used for a parity bit before the write of the next input video signal when the memory plane having the error is detected and applying similar switching at the read side. CONSTITUTION:If a fault takes place in any bit of (N+1) memory planes of an FMEM 6, at the time when its picture element is read, an error is detected in a PCHK 7, its detection signal is sent to an EPLDT 11, an address having an error is detected from the read address information of a RADG 14, the address information is stored and sent to a WADG 12. The circuit 12 sends a picture element designation signal to the SPNW 4, the circuit 4 replaces the parity bit and the N-bit of picture element information into bits of specific pattern, which is written in an address generating the error of the circuit 6. At the point of time of the read, the pattern is compared by the circuit 11, the error bit is detected and the erroneous memory plane is replaced into the memory plane used for the parity bit via a MCONT 15 and a SWA 5.