BIAS CIRCUIT IN FET COMPLEMENTARY COMPENSATION CIRCUIT

PURPOSE:To eliminate an output distortion by inserting a parallel circuit comprising a DC power supply and a resistor between a source of an N-channel FET and a source of a P-channel FET. CONSTITUTION:Sources of the N-channel FET1 and the P-channel FET2 are connected via a parallel circuit consistin...

Ausführliche Beschreibung

Bibliographische Detailangaben

1. Verfasser:	FUJIMAKI MASAKI
Format:	Patent
Sprache:	eng
Schlagworte:	AMPLIFIERS BASIC ELECTRONIC CIRCUITRY ELECTRICITY
Online-Zugang:	Volltext bestellen
Tags:	Tag hinzufügen Keine Tags, Fügen Sie den ersten Tag hinzu!