BIAS CIRCUIT IN FET COMPLEMENTARY COMPENSATION CIRCUIT

PURPOSE:To eliminate an output distortion by inserting a parallel circuit comprising a DC power supply and a resistor between a source of an N-channel FET and a source of a P-channel FET. CONSTITUTION:Sources of the N-channel FET1 and the P-channel FET2 are connected via a parallel circuit consisting of a DC constant voltage source 5 having a prescribed voltage value and of a series circuit of resistors 3, 4 giving a bias voltage. An input signal Vi is fed to a gate of each FET1, 2 and an output Vo is obtained from the connecting point between the resistors 3 and 4. Thus, the relation between the input voltage and the output voltage is expressed as a linear function to eliminate the output distortion.