PHASE LOCKED LOOP CIRCUIT

PURPOSE:To obtain a PLL circuit with less out-of-phase, less noise and a fast response speed by dividing a loop filter of the PLL circuit into a broad band filter and a narrow band filter, and switching them in response to the phase locked state. CONSTITUTION:The phase of an input signal 4 and that of an output signal 5 of a voltage controlled oscillator 3 oscillated in a self-running frequency are compared by a phase detector 1, an error signal is extracted and fed to a broad bad loop filter LF6 and a narrow band LF8. The error signal whose harmonics are rejected by the LF6 is added to an error signal whose harmonics are rejected by the LF8 via a low impedance amplifier 7 and a variable resistor 9 and the result is fed to a control input of the oscillator 3 via a buffer amplifier 10. When a lock detector 11 detects the state of unlocking, a resistor 9 is controlled to a minimum resistance value by using a switch signal 12, the output of the LF8 is made forcibly follow to the output of the LF6, the phase of the signal 4 is acquired by the high speed response by the LF6, and when the state reaches the lock state, the resistor 9 gets a high resistance and only the LF8 is activated.